Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Abstract: Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load

Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to the external tester. IEEE Standard 1500 provides efficient test infrastructure for testing digital cores; however, its applications in mixed-signal core test remain an open issue. In this paper we address the problem of implementing BIST of a mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and drawbacks of different test strategies. While the case study is focused on histogram based test of ADC, test strategies of other types of mixed-signal cores related to trade-off between performance (i.e., test time) and required resources are likely to follow similar conclusions

Functional Testing of Processor Cores in FPGA-Based Applications

Embedded processor cores, which are widely used in SRAM-based FPGA applications, are candidates for SEU (Single Event Upset)-induced faults and need to be tested occasionally during system exploitation. Verifying a processor core is a difficult task, due to its complexity and the lack of user knowledge about the core-implementation details. In user applications, processor cores are normally tested by executing some kind of functional test in which the individual processor's instructions are tested with a set of deterministic test patterns, and the results are then compared with the stored reference values. For practical reasons the number of test patterns and corresponding results is usually small, which inherently leads to low fault coverage. In this paper we develop a concept that combines the whole instruction-set test into a compact test sequence, which can then be repeated with different input test patterns. This improves the fault coverage considerably with no additional memory requirements

A Methodology For Model-Based Diagnosis Of Analog Circuits

In this paper we present a methodology for model-based diagnosis of analog circuits using the constraint logic programming approach. Presented methodology stems from our earlier work on the diagnosis of active analog filters by the artificial intelligence tool CLP(!) and has the following major improvements: modeling of the diagnosed circuit is generalized to arbitrary analog circuits consisting of linear elements (non-linear circuits are included by piecewise linearisation of their characteristics); both hard and parametric faults are considered in the diagnostic process; fault situations with multiple-hard-and-single-parametric faults can be diagnosed. Examples are given to illustrate the approach

Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load

On security issues of scan design

Abstract- Security problems of scan design are discussed and currently proposed solutions are investigated. Some conclusions related to their implementations in practice are drawn

Data Transmission Efficiency in Bluetooth Low Energy Versions

One important aspect when choosing a Bluetooth Low Energy (BLE) solution is to analyze its energy consumption for various connection parameters and desired throughput to build an optimal low-power Internet-of-Things (IoT) application and to extend the battery life. In this paper, energy consumption and data throughput for various BLE versions are studied. We have tested the effect of connection interval on the throughput and compared power efficiency relating to throughput for various BLE versions and different transactions. The presented results reveal that shorter connection intervals increase throughput for read/write transactions, but that is not the case for the notify and read/write without response transactions. Furthermore, for each BLE version, the energy consumption is mainly dependable on the data volume. The obtained results provide a design guideline for implementing an optimal BLE IoT application